The present invention relates generally to methods of forming trenches in wafers during fabrication of integrated circuits ("ICs"). More particularly, the invention relates to methods of forming high surface area trenches by etching through a substrate having chemically distinct strata.
Trenches in semiconductor substrates may serve various functions in integrated circuits. For example, trenches may electrically isolate MOS devices from one another on integrated circuits. They may also serve as part of a capacitor in "trench capacitor type" dynamic random access memory chips ("DRAMs"). In such DRAMs, each trench capacitor stores a single bit which may be either a 1 or a 0 depending upon whether the capacitor is charged or uncharged.
Trenches are particularly attractive for such applications because they utilize a substrate's third dimension (i.e., the direction normal to the substrate surface), and therefore occupy only very little area on the top surface of the substrate. While other structures for device isolation and capacitor formation can provide somewhat densely packed devices, trench-based structures generally require even less chip area. For example, when trenches are used for device isolation, they occupy far less area than the other commonly used major isolation structure: field oxides. Further, when trenches are used as capacitors in DRAMs, the trench capacitors occupy less substrate surface area than most other DRAM capacitor types (e.g., planar and stacked capacitors).
While trenches provide space saving advantages for certain applications, further improvements in device density may require trenches of increasing surface area. This is particularly true for trench capacitors in DRAM applications because each trench capacitor of a DRAM must be capable of storing a certain minimum amount of charge in order to ensure that information is not lost between refresh cycles. As the mount of stored charge in a trench type capacitor is directly proportional to the surface area of the trench itself, any surface area lost in narrowing the trench must be made up elsewhere. More generally, the capacitance of the trench capacitor must be maintained even as device sizes and spacing between devices decrease.
The capacitance of a trench capacitor may be increased in three ways. First, as noted, it may be increased by increasing the surface area of the capacitor plates (e.g., the trench walls). Second, it may be increased by increasing the dielectric constant of an insulator separating the plates, and finally, it may be increased by reducing the thickness of the insulator. While some work has focused on engineering trench dielectrics to be thinner dielectrics or have higher dielectric constants, such efforts are not particularly relevant to the invention described herein.
Some effort has focused on making narrow trench capacitors deeper so as to provide increased surface area. While this approach has yielded some improvements in device density, it is believed that to develop 64 megabit or greater trench-type DRAMs, trenches having submicron widths and aspect ratios of at least about 2.5 to 1 (depth to width) must be formed. However, trench capacitors in current 16 megabit DRAMs produced by Texas Instruments Corporation have widths of about 1.5 .mu.m and depths of only about 2.85 .mu.m. Unfortunately, available trench forming techniques have not yet proved able to reliably attain submicron trenches of the depth to width ratios necessary to reach the 64 megabit requirements.
Conventionally, trenches are formed by etching a masked substrate in a plasma reactor of some sort. Reactor conditions are chosen to produce anisotropic etching (i.e., etching that is primarily vertical, without significant lateral undercutting). The resulting trench has straight sidewalls extending vertically or nearly vertically down into the substrate (e.g., between about 80.degree. to 90.degree.). Conditions promoting such trenches include low reactor pressure, high bias for directing charged plasma species toward the substrate, and etch chemistries that provide protections of sidewalls.
Copending patent applications Ser. No. 08/531,727 (attorney docket no. LSI1PO36/P2585) entitled "INTEGRATED CIRCUIT DEVICE FABRICATION BY PLASMA ETCHING" and Ser. No. 08/531,473 (attorney docket no. LSI1PO33/P2586) entitled "INTEGRATED CIRCUIT DEVICE FABRICATION BY PLASMA ETCHING," both filed on Sep. 21, 1995 the same day as this application, and naming M. Rostoker as inventor (both incorporated herein by reference for all purposes) describe improved techniques for forming very deep and narrow trenches for use in trench capacitors. These applications describe plasma etching processes conducted in specialized reactors employing three or more electrodes and special etch conditions which protect trench sidewalls. The three electrodes provide improved control over the plasma uniformity and impact on the substrate. And the sidewall protection provides for a highly anisotropic etch and therefore a very deep and narrow trench. While such techniques represent improvements over the state of the art, it would be highly desirable have other techniques for maintaining the capacitance of trench capacitors as device size and spacing decrease.